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| 1 ? isl12026, isl12026a real time clock/ calendar with i 2 c bus? and eeprom the isl12026 and the isl12026a devices are micro power real time clocks with timing and crystal compensation, clock/calender, power-fail indicator, two periodic or polled alarms, intelligent battery backup switching, and integrated 512x8-bit eeprom configured in 16 bytes per page. the oscillator uses an external, low-cost 32.768khz crystal. the real time clock tracks time with separate registers for hours, minutes, and seconds. the device has calendar registers for date, month, ye ar and day of the week. the calendar is accurate through 2 099, with automatic leap year correction. the isl12026 and isl12026a have different types of power control settings. the isl12026 uses the legacy mode setting, which follows conditions set in x1226 products. the isl12026a uses the standard mode setting. please refer to ?power control operation? on page 13 for more details. also, please refer to ?i 2 c communications during battery backup? on page 22 for important details. pinouts isl12026, isl12026a (8 ld soic) top view isl12026, isl12026a (8 ld tssop) top view features ? real time clock/calendar - tracks time in hours, minutes and seconds - day of the week, day, month and year - 3 selectable frequency outputs ? two non-volatile alarms - settable on the second, minute, hour, day of the week, day or month - repeat mode (periodic interrupts) ? automatic backup to battery or supercap ? on-chip oscillator compensation - internal feedback resistor and compensation capacitors - 64 position digitally controlled trim capacitor - 6 digital frequency adjustment settings to 30ppm ? 512x8 bits of eeprom - 16-byte page write mode (32 total pages) - 8 modes of blocklock? protection - single byte write capability ? high reliability - data retention: 50 years - endurance: >2,000,000 cycles per byte ?i 2 c interface - 400khz data transfer rate ? 800na battery supply current ? package options - 8 ld soic and 8 ld tssop packages ? pb-free (rohs compliant) applications ? utility meters ? hvac equipment ? audio/video components ? set-top box/television ? modems ? network routers, hubs, switches, bridges ? cellular infrastructure equipment ? fixed broadband wireless equipment ? pagers/pda ? pos equipment ? test meters/fixtures ? office automation (copiers, fax) ? home appliances ? computer products ? other industrial/medical/automotive x1 x2 v bat v dd irq/ f out scl sda gnd 1 2 3 4 7 8 6 5 x1 x2 v bat v dd irq/ f out scl sda gnd 1 2 3 4 7 8 6 5 data sheet fn8231.9 november 30, 2010 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | copyright intersil americas inc. 2005, 2006, 2007, 2008, 2010. all rights reserved. intersil (and design) and blocklock are trademarks owned by intersil corporation or one of its subsidiaries. i 2 c bus? is a trademark owned by nxp semiconductors netherlands, b.v. all other trademarks mentioned are the property of their re spective owners.
2 fn8231.9 november 30, 2010 block diagram ordering information part number (notes 1, 2, 3) part marking v bat trip point (v) bsw bit default setting temp range (c) package (pb-free) pkg. dwg. # isl12026ibz 12026 ibz v dd < v bat bsw = 1 -40 to +85 8 ld soic m8.15 isl12026ivz 2026 ivz v dd < v bat bsw = 1 -40 to +85 8 ld tssop m8.173 isl12026aibz 12026a ibz 2.2 bsw = 0 -40 to +85 8 ld soic m8.15 isl12026aivz 2026a ivz 2.2 bsw = 0 -40 to +85 8 ld tssop m8.173 notes: 1. add ?-t*? suffix for tape and reel. please refer to tb347 for details on reel specifications. 2. these intersil pb-free plastic packaged produ cts employ special pb-free material sets , molding compounds/die attach materials , and 100% matte tin plate plus anneal (e3 terminat ion finish, which is rohs compliant and compatib le with both snpb and pb-free soldering opera tions). intersil pb- free products are msl classified at pb-free peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020. 3. for moisture sensitivity level (msl), please see device information page for isl12026, isl12026a . for more information on msl please see techbrief tb363 . x1 x2 oscillator frequency timer logic divider calendar 8 control/ registers 1hz time keeping registers alarm regs compare mask control decode logic alarm (eeprom) (eeprom) scl sda serial interface decoder 4k eeprom array registers status (sram) select irq/ f out v dd v bat 32.768khz (sram) battery circuitry switch osc compensation pin descriptions pin number symbol description soic tssop 1 3 x1 the x1 pin is the input of an inverting amplifier and is intended to be connected to one pin of an external 32.768khz quartz crystal. x1 can also be driven directly from a 32.768khz source (see ?application section? on page 19.) 2 4 x2 the x2 pin is the output of an inverting amplifier and is intended to be connected to one pin of an external 32.768khz quartz crystal (see ?application section? on page 19.) 35irq/ f out interrupt output/frequency output is a multi-functional pin that can be used as interrupt or frequency output pin. the function is set via the control re gister. this output is an open drain configuration. 4 6 gnd ground. 5 7 sda serial data (sda) is a bidirectional pin used to tr ansfer serial data into and out of the device. it has an open drain output and may be wire or?ed with other open drain or open collector outputs. 6 8 scl the serial clock (scl) input is used to clock all serial data into and out of the device. the input buffer on this pin is always active (not gated). 71v bat this input provides a backup supply voltage to the device. v bat supplies power to the device in the event that the v dd supply fails. this pin should be tied to ground if not used. 82v dd power supply. isl12026, isl12026a 3 fn8231.9 november 30, 2010 absolute maximum rati ngs thermal information voltage on v dd , v bat , scl, sda, and irq /f out pins (respect to ground) . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 6.0v voltage on x1 and x2 pins (respect to ground) . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 2.5v latchup (note 4) . . . . . . . . . . . . . . . . . . . class ii, level b @ +85c esd rating human body model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2kv machine model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175v thermal resistance (typical) ja (c/w) jc (c/w) 8 ld soic package (notes 5, 6) . . . . . 115 50 8 ld tssop package (notes 5, 6) . . . 140 48 storage temperature . . . . . . . . . . . . . . . . . . . . . . . .-65c to +150c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/pb-freereflow.asp caution: do not operate at or near the maximum ratings listed fo r extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 4. jedec class ii pulse condi tions and failure criterion used. level b exceptions are: using a max positive pulse of 8.35v on al l pins except x1 and x2, using a max positive pulse of 2.75v on x1 and x2, and using a max negative pulse of -1v for all pins. 5. ja is measured with the component mounted on a high effective therma l conductivity test board in free air. see tech brief tb379 f or details. 6. for jc , the ?case temp? location is taken at the package top center. dc electrical specifications unless otherwise noted, v dd = +2.7v to +5.5v, t a = -40c to +85c, typical values are @ t a = +25c and v dd = 3.3v. symbol parameter conditions min (note 16) typ max (note 16) unit notes v dd main power supply 2.7 5.5 v v bat backup power supply 1.8 5.5 v electrical specifications symbol parameter conditions min (note 16) typ max (note 16) unit notes i dd1 supply current with i 2 c active v dd = 2.7v 500 a 7, 8, 9 v dd = 5.5v 800 a i dd2 supply current for non-volatile programming v dd = 2.7v 2.5 ma 7, 8, 9 v dd = 5.5v 3.5 ma i dd3 supply current for main timekeeping (low power mode) v dd = v sda = v scl = 2.7v 10 a 9 v dd = v sda = v scl = 5.5v 20 a i bat battery supply current v bat = 1.8v, v dd = v sda = v scl = v reset = 0 800 1000 na 7, 10, 11 v bat = 3.0v, v dd = v sda = v scl = v reset = 0 850 1200 na i batlkg battery input leakage v dd = 5.5v, v bat = 1.8v 100 na v trip v bat mode threshold 1.8 2.2 2.6 v 11 v triphys v trip hysteresis 30 mv 11, 14 v bathys v bat hysteresis 50 mv 11, 14 v dd sr- v dd negative slew rate 10 v/ms 12 irq /f out v ol output low voltage v dd = 5v i ol = 3ma 0.4 v v dd = 1.8v i ol = 1ma 0.4 v i lo output leakage current v dd = 5.5v v out = 5.5v 100 400 na isl12026, isl12026a 4 fn8231.9 november 30, 2010 eeprom specifications parameter test conditions min (note 16) typ max (note 16) units notes eeprom endurance >2,000,000 cycles eeprom retention temperature + 75c 50 years serial interface (i 2 c) specifications dc electrical specifications symbol parameter test conditions min (note 16) typ max (note 16) units notes v il sda and scl input buffer low voltage -0.3 0.3xv dd v v ih sda and scl input buffer high voltage 0.7 x v dd v dd + 0.3 v hysteresis sda and scl input buffer hysteresis 0.05 x v dd v v ol sda output buffer low voltage i ol = 4ma 0 0.4 v i li input leakage current on scl v in = 5.5v 100 na i lo i/o leakage current on sda v in = 5.5v 100 na ac electrical specifications symbol parameter test conditions min (note 16) typ max (note 16) units notes f scl scl frequency 400 khz t in pulse width suppression time at sda and scl inputs any pulse narrower than the max spec is suppressed. 50 ns t aa scl falling edge to sda output data valid scl falling edge crossing 30% of v dd , until sda exits the 30% to 70% of v dd window. 900 ns t buf time the bus must be free before the start of a new transmission sda crossing 70% of v dd during a stop condition, to sda crossing 70% of v dd during the following start condition. 1300 ns t low clock low time measured at the 30% of v dd crossing. 1300 ns t high clock high time measured at the 70% of v dd crossing. 600 ns t su:sta start condition set-up time sc l rising edge to sda falling edge. both crossing 70% of v dd . 600 ns t hd:sta start condition hold time from sda falling edge crossing 30% of v dd to scl falling edge crossing 70% of v dd . 600 ns t su:dat input data set-up time from sda exiting the 30% to 70% of v dd window, to scl rising edge crossing 30% of v dd . 100 ns t hd:dat input data hold time from scl rising edge crossing 70% of v dd to sda entering the 30% to 70% of v dd window. 0ns isl12026, isl12026a 5 fn8231.9 november 30, 2010 timing diagrams bus timing t su:sto stop condition set-up time from scl rising edge crossing 70% of v dd , to sda rising edge crossing 30% of v dd . 600 ns t hd:sto stop condition hold time for read or volatile only write from sda rising edge to scl falling edge. both crossing 70% of v dd . 600 ns t dh output data hold time from scl falling edge crossing 30% of v dd , until sda enters the 30% to 70% of v dd window. 0ns cpin sda and scl pin capacitance 10 pf t wc non-volatile write cycle time 12 20 ms 14 t r sda and scl rise time from 30% to 70% of v dd 20 + 0.1xcb 300 ns t f sda and scl fall time from 70% to 30% of v dd 20 +0.1xcb 300 ns 15 cb capacitive loading of sda or scl total on-chip and off-chip 10 400 pf 15 r pu sda and scl bus pull-up resistor off-chip maximum is determined by t r and t f . for cb = 400pf, max is about 2k ~2.5k . for cb = 40pf, max is about 15k ~20k 1k 15 notes: 7. irq/ f out inactive. 8. v il = v dd x 0.1, v ih = v dd x 0.9, f scl = 400khz 9. v dd > v bat +v bathys 10. bit bsw = 0 (standard mode), atr = 00h, v bat 1.8v 11. specified at +25c. 12. in order to ensure proper timekeeping, the v dd sr- specification must be followed. 13. parameter is not 100% tested. 14. t wc is the minimum cycle time to be allowed for any non-volatile write by the user, it is the time from valid stop condition at the end of write sequence of a serial interface write operation, to the end of the self-timed internal non-volatile write cycle. 15. these are i 2 c specific parameters and are not directly tested, however th ey are used during device testing to validate device specification . 16. compliance to datasheet limits is assured by one or mo re methods: production test, c haracterization and/or design. ac electrical specifications (continued) symbol parameter test conditions min (note 16) typ max (note 16) units notes t su:sto t dh t high t su:sta t hd:sta t hd:dat t su:dat scl sda (input timing) sda (output timing) t f t low t buf t aa t r t hd:sto isl12026, isl12026a 6 fn8231.9 november 30, 2010 write cycle timing scl sda t wc 8th bit of last byte ack stop condition start condition typical performance curves temperature is +25c unl ess otherwise specified. figure 1. i bat vs v bat, sbib = 0 figure 2. i bat vs v bat, sbib = 1 figure 3. i dd3 vs temperature figure 4. i bat vs temperature 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 1.8 2.3 2.8 3.3 3.8 4.3 4.8 5.3 v bat (v) i bat (a) scl, sda pull-ups = 0v scl, sda pull-ups = v bat bsw = 0 or 1 bsw = 0 or 1 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.8 2.3 2.8 3.3 3.8 4.3 4.8 5.3 v bat (v) i bat (a) scl, sda pull-ups = 0v bsw = 0 or 1 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 -45-35-25-15-5 5 1525354555657585 temperature (c) i dd (a) v dd = 3.3v v dd = 5.5v 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 -45-35-25-15-5 5 1525354555657585 temperature (c) i bat (a) v bat = 3.0v isl12026, isl12026a 7 fn8231.9 november 30, 2010 description the isl12026 device is a real time clock with clock/ calendar, two polled alarms with integrated 512x8 eeprom, oscillator compensation and battery backup switch. the oscillator uses an external, low-cost 32.768khz crystal. all compensation and trim components are integrated on the chip. this eliminates several external discrete components and a trim capacitor, saving board area and component cost. the real time clock keeps tr ack of time with separate registers for hours, minutes and seconds. the calendar has separate registers for date, month, year and day-of-week. the calendar is correct thr ough 2099, with automatic leap year correction. the dual alarms can be set to any clock/calendar value for a match. for instance, every mi nute, every tuesday, or 5:23 am on march 21. the alarms can be polled in the status register or can provide a hardware interrupt (irq /f out pin). there is a pulse mode for the alarms allowing for repetitive alarm functionality. the irq /f out pin may be software selected to provide a frequency output of 1hz, 4096 hz, or 32,768hz or inactive. the device offers a backup power input pin. this v bat pin allows the device to be backed up by battery or supercap. the entire isl12026 device is full y operational from 2.7v to 5.5v and the clock/calendar por tion of the isl12026 device remains fully operational down to 1.8v (standby mode). the isl12026 device provides 4k bits of eeprom with 8 modes of blocklock? control. the blocklock? allows a safe, secure memory for critical user and configuration data, while allowing a large user storage area. pin descriptions serial clock (scl) the scl input is used to clock all data into and out of the device. the input buffer on this pin is always active (not gated). the pull-up resistor on this pin must use the same voltage source as v dd . serial data (sda) sda is a bidirectional pin used to transfer data into and out of the device. it has an open drain output and may be wire ored with other open drain or open collector outputs. the input buffer is always active (not gated). this open drain output requires the use of a pull-up resistor. the pull-up resistor on this pin must use the same voltage source as v dd . the output circuitry controls the fall time of the output signal with the use of a slope controlled pull-down. the circuit is designed to comply with 400khz i 2 c interface speed. v bat this input provides a backup supply voltage to the device. v bat supplies power to the device in the event the v dd supply fails. this pin can be connected to a battery, a supercap or tied to ground if not used. irq /f out (interrupt output/frequency output) this dual function pin can be used as an interrupt or frequency output pin. the irq /f out mode is selected via the frequency out control bits of the int register. ? interrupt mode. the pin provides an interrupt signal output. this signal notifies a host processor that an alarm has occurred and requests action. it is an open drain active low output. ? frequency output mode. the pin outputs a clock signal which is related to the crystal frequency. the frequency output is user selectable and enabled via the i 2 c bus. it is an open drain output. figure 5. i dd3 vs v dd figure 6. f out vs atr setting typical performance curves (continued) temperature is +25c unless otherwise specified. 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 1.82.32.83.33.84.34.85.3 v dd (v) i dd (a) -40 -20 0 20 40 60 80 -32 -28 -24 -20 -16 -12 -8 -4 0 4 8 12 16 20 24 28 atr setting ppm change from atr = 0 isl12026, isl12026a 8 fn8231.9 november 30, 2010 x1, x2 the x1 and x2 pins are the i nput and output, respectively, of an inverting amplifier. an external 32.768khz quartz crystal is used with the isl12026 to supply a timebase for the real time clock. internal compensation circuitry provides high accuracy over the operating temperature range from -40c to +85c. this oscillator compensation network can be used to calibrate the crystal timing accuracy over-temperature either durin g manufacturing or with an external temperature sensor and microcontroller for active compensation. x2 is intended to drive a crystal only, and should not drive any external circuit. real time clock operation the real time clock (rtc) uses an external 32.768khz quartz crystal to maintain an accurate internal representation of the second, minute, hour, day, date, month and year. the rtc has leap-year correction. the clock also corrects for months having fewer than 31 da ys and has a bit that controls 24 hour or am/pm format. when the isl12026 powers up after the loss of both v dd and v bat , the clock will not operate until at least one byte is written to the clock register. reading the real time clock the rtc is read by initiating a read command and specifying the address corresponding to the register of the real time clock. the rtc registers can then be read in a sequential read mode. since the clock r uns continuously and a read takes a finite amount of time, there is the possibility that the clock could change during the co urse of a read operation. in this device, the time is latc hed by the read command (falling edge of the clock on the ack bit prior to rtc data output) into a separate latch to avoid time changes during the read operation. the clock continues to run. alarms occurring during a read are unaffected by the read operation. writing to the real time clock the time and date may be set by writing to the rtc registers. rtc register shoul d be written only with page write. to avoid changing the current time by an incomplete write operation, write to the all 8 bytes in one write operation. when writing the rtc register s, the new time value is loaded into a separate buffer at the falling edge of the clock during the acknowledge. this new rtc value is loaded into the rtc register by a stop bi t at the end of a valid write sequence. an invalid write o peration aborts the time update procedure and the contents of th e buffer are discarded. after a valid write operation, the rtc will reflect the newly loaded data beginning with the next ?one second? clock cycle after the stop bit is written. the rtc continues to update the time while an rtc register write is in progress and the rtc continues to run during any non-volatile write sequences. accuracy of the real time clock the accuracy of the real time clock depends on the accuracy of the quartz crystal that is used as the time base for the rtc. since the resonant frequency of a crystal is temperature dependent, the rtc performance will also be dependent upon temperature. the frequency deviation of the crystal is a function of th e turnover temperature of the crystal from the crystal?s nominal frequency. for example, a >20ppm frequency deviation translates into an accuracy of >1 minute per month. these parameters are available from the crystal manufacturer. intersil?s rtc family provides on-chip crystal compensation networks to adjust load-capacitance to tune oscillator frequency from -34ppm to +80ppm when using a 12.5pf load crystal. for more detailed information, see ?application section? on page 19. clock/control registers (ccr) the control/clock registers are located in an area separate from the eeprom array and ar e only accessible following a slave byte of ?1101111x? and reads or writes to addresses [0000h:003fh]. the clock/control memory map has memory addresses from 0000h to 003fh. the defined addresses are described in the table 1. writing to and reading from the undefined addresses are not recommended. ccr access the contents of the ccr can be modified by performing a byte or a page write operation directly to any address in the ccr. prior to writing to the ccr (except the status register), however, the wel and rwel bits must be set using a three step process (see ?writing to the clock/control registers? on page 12). the ccr is divided into 5 sections. these are: 1. alarm 0 (8 bytes; non-volatile) 2. alarm 1 (8 bytes; non-volatile) 3. control (5 bytes; non-volatile) 4. real time clock (8 bytes; volatile) 5. status (1 byte; volatile) each register is read and written through buffers. the non-volatile portion (or the co unter portion of the rtc) is updated only if rwel is set and only after a valid write operation and stop bit. a sequential read or page write operation provides access to t he contents of only one section of the ccr per operation. access to another section requires a new operation. a read or writ e can begin at any address in the ccr. it is not necessary to set the rwel bit prior to writing the status register. see ?status register (sr)? on page 9. supports a single byte read or write only. continued reads or writes from this section terminates the operation. x1 x2 figure 7. recommended crystal connection isl12026, isl12026a 9 fn8231.9 november 30, 2010 the state of the ccr can be read by performing a random read at any address in the ccr at any time. this returns the contents of that register loca tion. additional registers are read by performing a sequenti al read. the read instruction latches all clock registers into a buffer, so an update of the clock does not change the time being read. a sequential read of the ccr will not result in the output of data from the memory array. at the end of a read, the master supplies a stop condition to end the operation and free the bus. after a read of the ccr, the address remains at the previous address +1 so the user can execute a current address read of the ccr and continue reading the next register. real time clock registers sc, mn, hr, dt, mo, yr: cl ock/calendar registers these registers depict bcd repr esentations of the time. as such, sc (seconds) and mn (minutes) range from 00 to 59, hr (hour) is 1 to 12 with an am or pm indicator (h21 bit) or 0 to 23 (with mil = 1), dt (date) is 1 to 31, mo (month) is 1 to 12, yr (year) is 0 to 99. dw: day of the week register this register provides a day of the week status and uses three bits dy2 to dy0 to represent the seven days of the week. the counter advances in the cycle 0-1-2-3-4-5-6-0-1- 2-? the assignment of a numerical value to a specific day of the week is arbitrary a nd may be decided by the system software designer. the default value is defined as ?0?. 24 hour time if the mil bit of the hr register is 1, the rtc uses a 24-hour format. if the mil bit is 0, the rtc uses a 12-hour format and h21 bit functions as an am/pm indicator with a ?1? representing pm. the clock defaults to standard time with h21 = 0. leap years leap years add the day februa ry 29 and are defined as those years that are divisible by 4. status register (sr) the status register is located in the ccr memory map at address 003fh. this is a volatile register only and is used to control the wel and rwel write enable latches, read power status and two alarm bits. this register is separate from both the array and the clock/control registers (ccr). bat: battery supply - volatile this bit set to ?1? indicates that the device is operating from v bat , not v dd . it is a read-only bit and is set/reset by hardware (isl12026 internally). once the device begins operating from v dd , the device sets this bit to ?0?. al1, al0: alarm bits - volatile these bits announce if either alarm 0 or alarm 1 match the real time clock. if there is a ma tch, the respective bit is set to ?1?. the falling edge of the last data bit in a sr read operation resets the flags. note: only the al bits that are set when an sr read starts will be reset. an alarm bit that is set by an alarm occurring during an sr read operation will remain set after the read operation is complete. oscf: oscillator fail indicator this bit is set to ?1? if the oscillator is not operating, or is operating, but has clock jitte r which does not affect the accuracy of rtc counting. the bit is set to ?0? if the oscillator is functioning, and does not have clock jitter. this bit is read only, and is set/reset by hardware. rwel: register write en able latch - volatile this bit is a volatile latch that powers up in the low (disabled) state. the rwel bit must be set to ?1? prior to any writes to the clock/control regist ers. writes to rwel bit do not cause a non- volatile write cycle, so the device is ready for the next operation immediately after the stop condition. a write to the ccr requires both the rwel and wel bits to be set in a specific sequence. wel: write enable latch - volatile the wel bit controls the access to the ccr during a write operation. this bit is a volatile latch that powers up in the low (disabled) state. while the wel bit is low, writes to the ccr address will be ignored, although acknowledgment is still issued. the wel bit is set by writing a ?1? to the wel bit and zeroes to the other bits of the status register. once set, wel remains set until either reset to 0 (by writing a ?0? to the wel bit and zeroes to the other bits of the status register) or until the part powers up again. writes to wel bit do not cause a non-volatile write cycle, so the device is ready for the next operation immediately after the stop condition. rtcf: real time clock fail bit - volatile this bit is set to a ?1? after a total power failure. this is a read only bit that is set by hardware (isl12026 internally) when the device powers up after having lost all power to the device (both v dd and v bat go to 0v). the bit is set regardless of whether v dd or v bat is applied first. the loss of only one of the supplies does not set the rtcf bit to ?1?. on power-up after a total power failure, all registers are set to their default states and the clock will not increment until at least one byte is written to the clock register. the first valid write to the rtc section after a complete power failure resets the rtcf bit to ?0? (writing one byte is sufficient). unused bits bit 3 in the sr is not used, but must be zero. the data byte output during a sr read will contain a zero in this bit location. table 1. status register (sr) addr 7 6 5 4 3 2 1 0 003fh bat al1 al0 oscf 0 rwel wel rtcf default 0 0 0 0 0 0 0 1 isl12026, isl12026a 10 fn8231.9 november 30, 2010 alarm registers (non-volatile) alarm0 and alarm1 the alarm register bytes are set up identical to the rtc register bytes, except that th e msb of each byte functions as an enable bit (enable = ?1?). these enable bits specify which alarm registers (seconds, minu tes, etc.) are used to make the comparison. note that there is no alarm byte for year. the alarm function works as a comparison between the alarm registers and the rtc registers. as the rtc advances, the alarm will be triggered once a match occurs between the alarm registers an d the rtc registers. any one alarm register, multiple registers, or all registers can be enabled for a match. see ?device operation? on page 12 and ?application section? on page 19 for more information. control registers (non-volatile) the control bits and registers described in the following are non-volatile. bl register bp2, bp1, bp0 - block protect bits the block protect bits, bp2, bp1 and bp0, determine which blocks of the array are write prot ected. a write to a protected block of memory is ignored. the block protect bits will prevent write operations to one of eight segments of the array. the partitions are described in table 3. table 2. clock/control memory map addr. type reg name bit range isl12026 default isl12026a default 76 5 4 3 2 1 0 003f status sr bat al1 al0 oscf 0 rwel wel rtcf 01h 01h 0037 rtc (sram) y2k 0 0 y2k21 y2k20 y2k13 0 0 y2k10 19/20 20h 20h 0036 dw 0 0 0 0 0 dy2 dy1 dy0 0-6 00h 00h 0035 yr y23 y22 y21 y20 y13 y12 y11 y10 0-99 00h 00h 0034 mo 0 0 0 g20 g13 g12 g11 g10 1-12 00h 00h 0033 dt 0 0 d21 d20 d13 d12 d11 d10 1-31 01h 01h 0032 hr mil 0 h21 h20 h13 h12 h11 h10 0-23 00h 00h 0031 mn 0 m22 m21 m20 m13 m12 m11 m10 0-59 00h 00h 0030 sc 0 s22 s21 s20 s13 s12 s11 s10 0-59 00h 00h 0014 control (eeprom) pwr sbib bsw 0 0 0 0 0 0 40h 00h 0013 dtr 0 0 0 0 0 dtr2 dtr1 dtr0 00h 00h 0012 atr 0 0 atr5 atr4 atr3 atr2 atr1 atr0 00h 00h 0011 int im al1e al0e fo1 fo0 0 0 0 00h 00h 0010 bl bp2 bp1 bp0 0 0 0 0 0 00h 00h 000f alarm1 (eeprom) y2k1 0 0 a1y2k21 a1y2k20 a1y2k13 0 0 a1y2k10 19/20 20h 20h 000e dwa1 edw1 0 0 0 0 dy2 dy1 dy0 0-6 00h 00h 000d yra1 unused - default = rtc year value (no eeprom) - future expansion 000c moa1 emo1 0 0 a1g20 a1g13 a1g12 a1g11 a1g10 1-12 00h 00h 000b dta1 edt1 0 a1d21 a1d20 a1d13 a1d12 a1d11 a1d10 1-31 00h 00h 000a hra1 ehr1 0 a1h21 a1h20 a1h13 a1h12 a1h11 a1h10 0-23 00h 00h 0009 mna1 emn1 a1m22 a1m21 a1m20 a1m13 a1m12 a1m11 a1m10 0-59 00h 00h 0008 sca1 esc1 a1s22 a1s21 a1s20 a1s13 a1s12 a1s11 a1s10 0-59 00h 00h 0007 alarm0 (eeprom) y2k0 0 0 a0y2k21 a0y2k20 a0y2k13 0 0 a0y2k10 19/20 20h 20h 0006 dwa0 edw0 0 0 0 0 dy2 dy1 dy0 0-6 00h 00h 0005 yra0 unused - default = rtc year value (no eeprom) - future expansion 0004 moa0 emo0 0 0 a0g20 a0g13 a0g12 a0g11 a0g10 1-12 00h 00h 0003 dta0 edt0 0 a0d21 a0d20 a0d13 a0d12 a0d11 a0d10 1-31 00h 00h 0002 hra0 ehr0 0 a0h21 a0h20 a0h13 a0h12 a0h11 a0h10 0-23 00h 00h 0001 mna0 emn0 a0m22 a0m21 a0m20 a0m13 a0m12 a0m11 a0m10 0-59 00h 00h 0000 sca0 esc0 a0s22 a0s21 a0s20 a0s13 a0s12 a0s11 a0s10 0-59 00h 00h isl12026, isl12026a 11 fn8231.9 november 30, 2010 int register: interrupt control and frequency output register im, al1e, al0e - interrupt control and status bits there are two interrupt control bits, alarm 1 interrupt enable (al1e) and alarm 0 interrupt enable (al0e) to specifically enable or disable the alarm interrupt signal output (irq /f out ). the interrupts are enabled when either the al1e or al0e or both bits are set to ?1? and both the fo1 and fo0 bits are set to 0 (f out disabled). the im bit enables the pulsed interrupt mode. to enter this mode, the al0e or al1e bits are set to ?1?, and the im bit to ?1?. the irq/ f out output will now be pulsed each time an alarm occurs. this means that once the interrupt mode alarm is set, it will continue to alarm for each occurring match of the alarm and present time. this m ode is convenient for hourly or daily hardware interrupts in micr ocontroller applications such as security cameras or utility meter reading. in the case that both alarm 0 and alarm 1 are enabled, the irq /f out pin will be pulsed each time either alarm matches the rtc (both alarms can provid e hardware interrupt). if the im bit is also set to "1", the irq /f out will be pulsed for each of the alarms as well. fo1, fo0 - programmable frequency output bits these are two output control bi ts. they select one of three divisions of the internal oscill ator, that is applied to the irq /f out output pin. table 4 shows the selection bits for this output. when using this function, the alarm output function is disabled. oscillator compensation registers there are two trimming options. ? atr. analog trimming register ? dtr. digital trimming register these registers are non-volatile. the combination of analog and digital trimming can give up to -64 to +110 ppm of total adjustment. atr register - atr5, atr4, atr3, atr2, atr1, atr0: analog trimming register 6 analog trimming bits, atr0 to atr5, are provided in order to adjust the on-chip load capacitance value for frequency compensation of the rtc. each bit has a different weight for capacitance adjustment. for ex ample, using a citizen cfs- 206 crystal with different atr bit combinations provides an estimated ppm adjustment range from -34 to +80ppm to the nominal frequency compensation. the effective on-chip series load capacitance, c load , ranges from 4.5pf to 20.25pf with a mid-scale value of 12.5pf (default). c load is changed via two digitally controlled capacitors, c x1 and c x2 , connected from the x1 and x2 pins to ground (see figure 8). the value of c x1 and c x2 is given by equation 1: the effective series load capacitance is the combination of c x1 and c x2 : for example, c load (atr = 00000) = 12.5pf, c load (atr = 100000) = 4.5pf, and c load (atr = 011111) = 20.25pf. the entire range for the series combination of load capacitance goes from 4.5pf to 20.25pf in 0.25pf steps. note that these are typical values. table 3. bp2 bp1 bp0 protected addresses isl12026 array lock 0 0 0 none (default) none 0 0 1 180 h ? 1ff h upper 1/4 0 1 0 100 h ? 1ff h upper 1/2 0 1 1 000 h ? 1ff h full array 100 000 h ? 03f h first 4 pages 101 000 h ? 07f h first 8 pages 1 1 0 000 h ? 0ff h first 16 pages 1 1 1 000 h ? 1ff h full array table 4. programmable frequency output bits fo1 fo0 output frequency 0 0 alarm output (f out disabled) 0 1 32.768khz 1 0 4096hz 11 1hz figure 8. diagram of atr c x1 x1 x2 crystal oscillator c x2 c x 16 b5 ? 8b4 4b3 2b2 1b1 0.5b0 9 + ? + ? + ? + ? + ? + () pf = (eq. 1) c load 1 1 c x1 ---------- - 1 c x2 ---------- - + ?? ?? ---------------------------------- - = c load 16 b5 ? 8 b4 4 b3 2 b2 1 b1 0.5 b0 9 + ? + ? + ? + ? + ? + 2 ----------------------------------------------------------------------------------------------------------------------------- ?? ?? pf = (eq. 2) isl12026, isl12026a 12 fn8231.9 november 30, 2010 dtr register - dtr2, dtr1, dtr0: digital trimming register the digital trimming bits dtr2, dtr1 and dtr0 adjust the number of counts per second and average the ppm error to achieve better accuracy. dtr2 is a sign bit. dtr2 = 0 means frequency compensation is > 0. dtr2 = 1 means frequency compensation is < 0. dtr1 and dtr0 are scale bits. dtr1 gives 10 ppm adjustment and dtr0 gives 20 ppm adjustment. a range from -30ppm to +30ppm can be represented by using the three dtr bits. pwr register: sbib, bsw sbib: - serial bus interface (enable) the serial bus can be disabled in battery backup mode by setting this bit to ?1?. this will minimize power drain on the battery. the serial interface can be enabled in battery backup mode by setting this bit to ?0?. (default is ?0?). see ?bsw: power control bit? on page 12. bsw: power control bit the power control bit, bsw, determines the conditions for switching between v dd and backup battery. there are two options. option 1. standard mode: set ?bsw = 0? option 2. legacy mode: set ?bsw = 1? see ?power control operation? on page 13 for more details. also see ?i 2 c communications during battery backup? on page 22 for important details. device operation writing to the clock/control registers changing any of the bits of the clock/control registers requires the following steps: 1. write a 02h to the status register to set the write enable latch (wel). this is a volatile operation, so there is no delay after the write (operat ion preceded by a start and ended with a stop). 2. write a 06h to the status regi ster to set both the register write enable latch (rwel) and the wel bit. this is also a volatile cycle. the zeros in the data byte are required (operation proceeded by a start and ended with a stop). write all 8 bytes to the rtc registers, or one byte to the sr, or one to five bytes to the c ontrol registers. this sequence starts with a start bit, requires a slave byte of ?11011110? and an address within the ccr and is terminated by a stop bit. a write to the eeprom registers in the ccr will initiate a non- volatile write cycle and will take up to 20ms to complete. a write to the rtc registers (sram) will require much shorter cycle time (t = t buf ). writes to undefined areas have no effect. the rwel bit is reset by the completion of a write to the ccr, so the sequence must be repeated to again initiate another change to the ccr contents. if the sequence is not completed for any reason (by sending an incorrect number of bits or sending a start inst ead of a stop, for example), the rwel bit is not reset and the device remains in an active mode. writing all zeros to the status register resets both the wel and rwel bits. a read operation occurring between any of the previous operations will not interrupt the register write operation. alarm operation since the alarm works as a comparison between the alarm registers and the rtc registers, it is ideal for notifying a host processor of a particular time event, which triggers some action as a result. the host can be notified by either a hardware interrupt (the irq /f out pin) or by polling the status register (sr) alarm bits. these two volatile bits (al1for alarm 1 and al0 for alarm 0), indicate if an alarm has happened. the bits are set on an alarm condition regardless of whether the irq /f out interrupt is enabled. the al1 and al0 bits in the status register are reset by the falling edge of the eighth clock of status register read. there are two alarm operation modes: single event and periodic interrupt mode: 1. single event mode is enabled by setting the al0e or al1e bit to ?1?, the im bit to ?0?, and disabling the frequency output. this mode permits a one-time match between the alarm registers and the rtc registers. once this match occurs, the al0 or al1 bit is set to ?1? and the irq/ f out output will be pulled low and will remain low until the al0 or al1 bit is read, which will automatically resets it. both alarm registers can be set at the same time table 5. digital trimming registers dtr register estimated frequency ppm dtr2 dtr1 dtr0 000 0 010 +10 001 +20 011 +30 100 0 110 -10 101 -20 111 -30 table 6. v bat trip point with different bsw setting bsw bit v bat trip point (v) power control setting 0 2.2 standard mode (isl12026a) 1v dd < v bat legacy mode (isl12026) isl12026, isl12026a 13 fn8231.9 november 30, 2010 to trigger alarms. the irq/ f out output will be set by either alarm, and will need to be cleared to enable triggering by a subsequent alarm. polling the sr will reveal which alarm has been set. 2. interrupt mode (or ?pulsed interrupt mode? or pim) is enabled by setting the al0e or al1e bit to ?1? the im bit to ?1?, and disabling the fr equency output. if both al0e and al1e bits are set to "1", then both al0e and al1e pim alarms will function. the irq /f out output will now be pulsed each time each of the alarms occurs. this means that once the interrupt mode alarm is set, it will continue to alarm for each occurring match of the alarm and present time. this mode is convenient for hourly or daily hardware interrupts in microcontroller applications such as security cameras or utility meter reading. interrupt mode cannot be used for general periodic alarms, however, since a specific time period cannot be programmed for interrupt, only matches to a specific time of day. the interrupt mode is only stopped by disabling the im bit or the alarm enable bits. writing to the alarm registers the alarm registers are non-v olatile but require special attention to insure a proper non-volatile write takes place. specifically, byte writes to individual registers are good for all but registers 0006h and 0000eh, which are the dwa0 and dwa1 registers, respectively. those registers will require a special page write for non-volatile storage. the recommended page write sequences are as follows: 1. 16-byte page writes: the best way to write or update the alarm registers is to perform a 16-byte write beginning at address 0001h (mna0) and wrapping around and ending at address 0000h (sca0). this will insure that non-volatile storage takes pl ace. this means that the code must be designed so that the alarm0 data is written starting with minutes register, and then all the alarm1 data, with the last byte being the alarm0 seconds (the page ends at the alarm1 y2k register and then wraps around to address 0000h). alternatively, the 16-byte page write could start with address 0009h, wrap around and finish with address 0008h. note that any page write ending at address 0007h or 000fh (the highest byte in each alarm) will not trigger a non-volatile write, so wrapping around or overlapping to the following alarm's seconds register is advised. 2. other non-volatile writes: it is possible to do writes of less than an entire page, but the final byte must always be addresses 0000h through 0004h or 0008h though 000ch to trigger a non-volat ile write. writing to those blocks of 5 bytes sequentially, or individually, will trigger a non-volatile write. if the dwa0 or dwa1 registers need to be set, then enough bytes will need to be written to overlap with the other alarm register and trigger the non-volatile write. for example, if the dwa0 register is being set, then the code can start with a multiple byte write beginning at address 0006h, and then write 3 bytes ending with the sca1 register as follows: addr name 0006h dwa0 0007h y2k0 0008h sca1 if the alarm1 is used, sca1 would need to have the correct data written. power control operation the power control circuit accepts a v dd and a v bat input. many types of batteries can be used with intersil rtc products. for example, 3.0v or 3.6v lithium batteries are appropriate, and battery sizes are available that can power an intersil rtc device for up to 10 years. another option is to use a supercap for applications where v dd is interrupted for up to a month. see ?application section? on page 19 for more information. there are two options for setting the change-over conditions from v dd to battery backup mode. the bsw bit in the pwr register controls this operation: ? option 1 - standard mode (isl12026a default) ? option 2 - legacy mode (isl12026 default) note that the i 2 c bus may or may not be operational during battery backup. that function is controlled by the sbib bit. that operation is covered af ter the power control section. option 1- standard power control mode (isl12026a default) in the standard mode, the supply will switch over to the battery when v dd drops below v trip or v bat , whichever is lower. in this mode, accidental operation from the battery is prevented since the battery bac kup input will only be used when the v dd supply is shut off. to select option 1, bsw bit in the power register must be set to ?bsw = 0?. a description of power switchover follows. standard mode power switchover ? normal operating mode (v dd ) to battery backup mode (v bat ) to transition from the v dd to v bat mode, both of the following conditions must be met: - condition 1: v dd < v bat - v bathys where v bathys 50mv - condition 2: v dd < v trip where v trip 2.2v ? battery backup mode (v bat ) to normal mode (v dd ) isl12026, isl12026a 14 fn8231.9 november 30, 2010 the isl12026 device will switch from the v bat to v dd mode when one of the following conditions occurs: - condition 1: v dd > v bat + v bathys where v bathys 50mv - condition 2 : v dd > v trip + v triphys where v triphys 30mv there are two discrete situati ons that are possible when using standard mode: v bat < v trip and v bat > v trip . these two power control situations are illustrated in figures 9 and 10. option 2 -legacy power control mode (isl12026 default) the legacy mode follows conditions set in x1226 products. in this mode, switching from v dd to v bat is simply done by comparing the voltages and the device operates from whichever is the higher voltage. care should be taken when changing from normal to legacy mode. if the v bat voltage is higher than v dd , then the device will enter battery back up and unless the battery is disconnected or the voltage decreases, the device will no longer operate from v dd . to select the option 2, bsw bi t in the power register must be set to ?bsw = 1? ? normal mode (v dd ) to battery backup mode (v bat ) to transition from the v dd to v bat mode, the following conditions must be met: v dd < v bat - v bathys ? battery backup mode (v bat ) to normal mode (v dd ) the device will switch from the v bat to v dd mode when the following condition occurs: v dd > v bat +v bathys the legacy mode power control conditions are illustrated in figure 11. serial communication the device supports the i 2 c protocol. clock and data data states on the sda line can change only during scl low. sda state changes during scl high are reserved for indicating start and stop conditions (see figure 12). start condition all commands are preceded by the start condition, which is a high to low transition of sda when scl is high. the device continuously monitors the sda and scl lines for the start condition and will not respond to any command until this condition has been met (see figure 13). stop condition all communications must be terminated by a stop condition, which is a low to high transition of sda when scl is high. the stop condition is also used to place the device into the standby power mode after a read sequence. a stop condition can only be issued after the transmitting device has released the bus (see figure 13). acknowledge acknowledge is a software convention used to indicate successful data transfer. the transmitting device, either master or slave, will release the bus after transmitting 8 bits. during the ninth clock cycle, th e receiver will pull the sda line low to acknowledge that it received the 8 bits of data (see figure 14). the device will respond with an acknowledge after recognition of a start condition and if the correct device identifier and select bits are contained in the slave address byte. if a write oper ation is selected, the device will respond with an acknowledge after the receipt of each subsequent 8-bit word. the device will not acknowledge if the slave address byte is incorrect. battery backup mode v dd 2.2v figure 9. battery switchover when v bat < v trip v bat v trip 1.8v v bat + v bathys v bat - v bathys figure 10. battery switchover when v bat > v trip v trip v bat v trip + v triphys battery backup mode v dd v trip 3.0v 2.2v v bat in voltage v dd on off figure 11. battery switchover in legacy mode isl12026, isl12026a 15 fn8231.9 november 30, 2010 in the read mode, the device will transmit 8 bits of data, release the sda line, then monitor the line for an acknowledge. if an acknowledge is detected and no stop condition is generated by the master, the device will continue to transmit data. the device will terminate further data transmissions if an acknowledg e is not detected. the master must then issue a stop condition to return the device to standby mode and place the device into a known state. device addressing following a start condition, the master must output a slave address byte. the first 4 bits of the slave address byte specify access to either the eeprom array or to the ccr. slave bits ?1010? access the eeprom array. slave bits ?1101? access the ccr. when shipped from the factory, eeprom array is undefined, and should be programmed by the customer to a known state. bit 3 through bit 1 of the slave byte specifies the device select bits. these are set to ?111?. the last bit of the slave address byte defines the operation to be performed. when this r/w bit is a one, then a read operation is selected. a zero selects a write operation (see figure 15). after loading the entire slave address byte from the sda bus, the isl12026 compares the device identifier and device select bits with ?1010111? or ?1101111?. upon a correct compare, the device outputs an acknowledge on the sda line. scl sda data stable data change data stable figure 12. valid data changes on the sda bus scl sda start stop figure 13. valid start and stop conditions scl from master data output from transmitter data output from receiver 8 1 9 start acknowledge figure 14. acknowledge response from receiver isl12026, isl12026a 16 fn8231.9 november 30, 2010 following the slave byte is a two byte word address. the word address is either supplied by the master device or obtained from an internal counter. on power up the internal address counter is set to addr ess 0h, so a current address read of the eeprom array starts at address 0. when required, as part of a random read, the master must supply the 2 word address bytes as shown in figure 15. in a random read operation, t he slave byte in the ?dummy write? portion must match t he slave byte in the ?read? section. that is if the random read is from the array the slave byte must be 1010111x in both instances. similarly, for a random read of the clock/contro l registers, the slave byte must be 1101111x in both places. write operations byte write for a write operation, the device requires the slave address byte and the word address by tes. this gives the master access to any one of the words in the array or ccr. (note: prior to writing to the ccr, the master must write a 02h, then 06h to the status register in two preceding operations to enable the write operat ion. see ?writing to the clock/control registers? on page 12). upon receipt of each address byte, the isl12026 responds with an acknowledge. after receiving both address bytes the isl12026 awaits the 8 bits of data. after receiving the 8 data bits, the isl12026 again responds with an acknowledge. the ma ster then terminates the transfer by generating a stop condition. the isl12026 then begins an internal write cycle of the data to the non-volatile memory. during the internal write cycle, the device inputs are disabled, so the device will not respond to any requests from the master. the sda output is at high impedance (see figure 16). a write to a protected block of me mory is ignored, but will still receive an acknowledge. at the end of the write command, the isl12026 will not initiate an internal write cycle, and will continue to ack commands. byte writes to all of the non-volatile registers are allowed, except the dwan registers which require multiple byte writes or page writes to trigger non-volatile writes. see ?device operation? on page 12 for more information. page write the isl12026 has a page write operation. it is initiated in the same manner as the byte wr ite operation; but instead of terminating the write cycle afte r the first data byte is transferred, the master can tran smit up to 15 more bytes to the memory array and up to 7 mo re bytes to the clock/control registers. the rtc registers require a page write (8 bytes), slave address byte byte 0 d7 d6 d5 d2 d4 d3 d1 d0 a0 a7 a2 a4 a3 a1 data byte byte 3 a6 a5 00 0 0 0a8 0 1 1 0 1 1 0 1 0 1 1 r/w 1 device identifier array ccr 0 word address 1 byte 1 word address 0 byte 2 figure 15. slave address, word address, and data bytes (16 byte pages) s t a r t s t o p slave address word address 1 data a c k a c k a c k sda bus signals from the slave signals from the master 0 a c k word address 0 1 1 1 1 0000000 figure 16. byte write sequence isl12026, isl12026a 17 fn8231.9 november 30, 2010 individual register writes are not allowed. (note: prior to writing to the ccr, the master must write a 02h, then 06h to the status register in two pr eceding operations to enable the write operation. see ?writing to the clock/control registers? on page 12). after the receipt of each byte, the isl12026 responds with an acknowledge, and the address is internally incremented by one. the address pointer re mains at the last address byte written. when the counter reac hes the end of the page, it ?rolls over? and goes back to the first address on the same page. this means that the ma ster can write 16 bytes to a memory array page or 8 bytes to a ccr section starting at any location on that page. for example, if the master begins writing at location 10 of the memory and loads 15 bytes, then the first 6 bytes are written to addresses 10 through 15, and the last 6 bytes are written to columns 0 through 5. afterwards, the address counter would point to location 6 on the page that was just written. if the master supplies more than the maximum bytes in a page, then the previously loaded data is over-written by the new data, one byte at a time. refer to figure 18. the master terminates the data byte loading by issuing a stop condition, which causes the isl12026 to begin the non-volatile write cycle. as with the byte write operation, all inputs are disabled until completion of the internal write cycle. refer to figure 17 for the address, acknowledge, and data transfer sequence. stops and write modes stop conditions that terminate write operations must be sent by the master after sending at least 1 full data byte and it?s associated ack signal. if a stop is issued in the middle of a data byte, or before 1 full dat a byte + ack is sent, then the isl12026 resets itself without performing the write. the contents of the array are not affected. word address 0 s t a r t s t o p slave address word address 1 data (n) a c k a c k a c k sda bus signals from the slave signals from the master 0 data (1) a c k 1 n 16 for eeprom array 1 n 8 for ccr 1 1 1 1 0000000 figure 17. page write sequence address address 10 6 bytes 15 6 bytes address = 5 address pointer ends figure 18. writing 12 bytes to a 16-b yte memory page starting at address 10 at addr = 5 isl12026, isl12026a 18 fn8231.9 november 30, 2010 acknowledge polling disabling of the inputs during non-volatile write cycles can be used to take advantage of th e 12ms (typ) write cycle time. once the stop condition is issued to indicate the end of the master?s byte load operation, the isl12026 initiates the internal non-volatile write cycle. acknowledge polling can begin immediately. to do this, the master issues a start condition followed by the memory array slave address byte for a write or read operation (aeh or afh). if the isl12026 is still busy with the non-volatile write cycle then no ack will be returned. when the isl12026 has completed the write operation, an ack is returned and the host can proceed with the read or write operation. re fer to the flow chart in figure 20. note: do not use the ccr slave byte (deh or dfh) for acknowledge polling. read operations there are three basic read operations: current address read, random read and sequential read. current address read internally the isl12026 contai ns an address counter that maintains the address of the last word read incremented by one. therefore, if the last r ead was to address n, the next read operation would access data from address n + 1. on power-up, the 16-bit address is initialized to 00h. in this way, a current address read immediately after the power on reset can download the entire contents of memory starting at the first location. upon receipt of the slave address byte with the r/w bit set to one, the isl12026 issues an acknowledge, then transmits 8 data bits. the master terminates the read operation by not responding with an acknowledge during the ninth clock and issuing a stop condition. refer to figure 19 for the address, acknowledge, and data transfer sequence. it should be noted that the ninth clock cycle of the read operation is not a ?don?t care.? to terminate a read operation, the master must either issue a stop condition during the ninth cycle or hold sda high during the ninth clock cycle and then issue a stop condition. random read random read operations allow the master to access any location in the isl12026. prior to issuing the slave address byte with the r/w bit set to zero, th e master must first perform a ?dummy? write operation. the master issues the start condition and the slave address byte, receives an acknowledge, then issues the word address bytes. after acknowledging receipt of each word address byte, the master immediately issues another start condition and the slave address byte with the r/w bit set to one. this is followed by an acknowledge from the device and then by the 8-bit data word. the master terminates the read operation by not responding with an acknowledge and then issuing a stop condition. refer to figure 21 for the address, acknowledge and data transfer sequence. in a similar operation called ?set current address,? the device sets the address if a stop is issued instead of the second start shown in figure 21. the isl12026 then goes into standby mode after the stop and all bus activity will be ignored until a start is detected. this operation loads the new address into the address counter. the next current address read operation will read from the newly loaded address. this operation could be useful if the master knows the next address it needs to read, but is not ready for the data. s t a r t s t o p slave address data a c k sda bus signals from the slave signals from the master 1 1 1 1 1 figure 19. current address read sequence figure 20. acknowledge polling sequence ack returned? issue memory array slave address byte afh (read) or aeh (write) byte load completed by issuing stop. enter ack polling issue stop issue start no yes issue stop no continue normal read or write command sequence proceed yes non-volatile write cycle complete. continue command sequence? isl12026, isl12026a 19 fn8231.9 november 30, 2010 sequential read sequential reads can be initiate d as either a current address read or random address read. the first data byte is transmitted as with the other modes; however, the master now responds with an acknowledge, indicating it requires additional data. the device continues to output data for each acknowledge received. the master terminates the read operation by not responding with an acknowledge and then issuing a stop condition. the data output is sequential, with the data from address n followed by the data from address n + 1. the address counter for read operations increments through all page and column addresses, allowing the entire memory contents to be serially read during one operation. at the end of the address space, the counter ?rolls over? to the start of the address space, and the isl12026 continues to output data for each acknowledge received. refer to figure 22 for the acknowledge and data transfer sequence. application section crystal oscillator and temperature compensation intersil has now integrated the oscillator compensation circuity on-chip, to eliminate the need for external components and adjust for crysta l drift over temperature and enable very high accuracy time keeping (<5ppm drift). the intersil rtc family uses an oscillator circuit with on-chip crystal compensation network, including adjustable load-capacitance. the only ex ternal component required is the crystal. the compensatio n network is optimized for operation with certain crystal parameters which are common in many of the surface mount or tuning-fork crystals available today. table 7 summarizes these parameters. table 8 contains some crystal manufacturers and part numbers that meet the requirements for the intersil rtc products. 0 slave address word address 1 a c k a c k s t a r t s t o p slave address data a c k 1 s t a r t sda bus signals from the slave signals from the master a c k word address 0 1 1 1 1 1 1 11 0000000 figure 21. random address read sequence data (2) s t o p slave address data (n) a c k a c k sda bus signals from the slave signals from the master 1 data (n-1) a c k a c k (n is any integer greater than 1) data (1) figure 22. sequential read sequence table 7. crystal parameters required for intersil rtcs parameter min typ max units notes frequency 32.768 khz frequency to l e r a n c e 100 ppm down to 20ppm if desired turnover temperature 20 25 30 c typically the value used for most crystals operating temp range -40 85 c parallel load capacitance 12.5 pf equivalent series resistance 50 k for best oscillator performance isl12026, isl12026a 20 fn8231.9 november 30, 2010 the turnover temperature in table 7 describes the temperature where the apex of the of the drift vs temperature curve occurs. this curve is parabolic with the drift increasing as (t - t0) 2 . for an epson mc-405 device, for example, the turnover temperature is typica lly +25c, and a peak drift of >110ppm occurs at the temperature extremes of -40c and +85c. it is possible to address this variable drift by adjusting the load capacitance of the crystal, which will result in predictable change to the crystal frequency. the intersil rtc family allows this adjustment over temperature since the devices include on-chip load capacitor trimming. this control is handled by the analog trimming register, or atr, which has 6-bits of control. the load capacitance range covered by the atr circuit is approximately 3.25pf to 18.75pf, in 0.25pf increments. note that actual capacitance would also include about 2pf of package re lated capacitance. in-circuit tests with commercially availabl e crystals demonstrate that this range of capacitance allows frequency control from +80ppm to -34ppm, using a 12.5pf load crystal. in addition to the analog compensation afforded by the adjustable load capacitance, a digital compensation feature is available for the intersil rtc family. there are 3-bits known as the digital trimming register or dtr, and they operate by adding or skipping pulses in the clock signal. the range provided is 30ppm in increments of 10ppm. the default setting is 0ppm. the dtr control can be used for coarse adjustments of frequency drift over-temperature or for crystal initial accuracy correction. a final application for the atr control is in-circuit calibration for high accuracy applications, along with a temperature sensor chip. once the rtc circuit is powered up with battery backup, the irq /f out output is set at 32.768khz and frequency drift is measured. the atr control is then adjusted to a setting which minimizes drift. once adjusted at a particular temperature, it is possible to adjust at other discrete temperatures for minima l overall drift, and store the resulting settings in the eeprom. extremely low overall temperature drift is possible wi th this method. the intersil evaluation board contains t he circuitry necessary to implement this control. layout considerations the crystal input at x1 has a very high impedance and will pick up high frequency signals from other circuits on the board. since the x2 pin is tied to the other side of the crystal, it is also a sensitive node. these signals can couple into the oscillator circuit and produce double clocking or mis-clocking, seriously affect ing the accuracy of the rtc. care needs to be taken in layout of the rtc circuit to avoid noise pickup. in figure 23 is a suggested layout for the isl12026 or isl12027 devices in 8 ld so package. the x1 and x2 connections to the crystal are to be kept as short as possible. a thick ground trace around the crystal is advised to minimize noise intrusion, but ground near the x1 and x2 pins should be avoided as it will add to the load capacitance at those pins. keep in mind these guidelines for other pcb layers in the vicinity of the rtc device. a small decoupling capacitor at the v dd pin of the chip is mandatory, with a solid connection to ground. the isl12026 product has a s pecial consideration. the irq /f out - pin on the 8 ld soic package is located next to the x2 pin. when this pin is used as a frequency output (irq /f out ) and is set to 32.768khz, noise can couple to the x1 or x2 pins and cause double-clocking. the layout in figure 23 minimizes this by running the irq /f out output away from the x1 and x2 pins. also, reducing the switching current at this pin by careful selection of the pull-up resistor value will reduce noise. intersil suggests a minimum value of 5.1k for 32.768khz, and higher values (up to 20k ) for lower frequency irq /f out outputs. for other rtc products, the same rules previously stated should be observed, but sl ightly adjusted since the packages and pinouts are different. oscillator measurements when a proper crystal is selected and the layout guidelines above are observed, the oscill ator should start-up in most table 8. crystal manufacturers manufacturer part number temp range (c) +25c freq. tolerance (ppm) citizen cm201, cm202, cm200s -40 to +85 20ppm epson mc-405, mc-406 -40 to +85 20ppm raltron rsm-200s-a or b -40 to +85 20ppm saronix 32s12a or b -40 to +85 20ppm ecliptek ecpsm29t-32.768k -10 to +60 20ppm ecs ecx-306/ecx-306i -10 to +60 20ppm fox fsm-327 -40 to +85 20ppm figure 23. suggested layout for intersil rtc in so-8 r5 47k x1 u1 isl12026, isl12026a 21 fn8231.9 november 30, 2010 circuits in less than one seco nd. some circuits may take slightly longer, but start-up should definitely occur in less than 5 seconds. when testing rtc circuits, the most common impulse is to apply a scope probe to the circuit at the x2 pin (oscillator output) and observe the waveform. do not do this! although in some cases you may see a usable waveform, due to the parasitics (usually 10pf to ground) applied with the scope probe, there will be no useful information in that waveform other than the fact that the circuit is oscillating. the x2 output is sensitive to capacitive impedance so the voltage levels and the frequency will be affected by the parasitic elements in the scope probe. applying a scope probe can possi bly cause a faulty oscillator to start up, hiding other issues (although in the intersil rtcs, the internal circuitry assures start-up when using the proper crystal and layout). the best way to analyze the rtc circuit is to power it up and read the real time clock as time advances, or if the chip has the irq /f out output, look at the ou tput of that pin on an oscilloscope (after enabling it with the control register, and using a pull-up resistor for an open-drain output). alternatively, the isl12026 device has an irq /f out output, which can be checked by setting an alarm for each minute. using the pulse interrupt mode setting, the once-per-minute interrupt functions as an indication of proper oscillation. backup battery operation many types of batteries can be used with the intersil rtc products. 3.0v or 3.6v lithiu m batteries are appropriate, and sizes are available that can power a intersil rtc device for up to 10 years. another option is to use a supercap for applications where v dd may disappear intermittently for short periods of time. depending on the value of supercap used, backup time can last from a few days to two weeks (with >1f). a simple silicon or schottky barrier diode can be used in series with v dd to charge the supercap, which is connected to the v bat pin. try to use schottky diodes with very low leakages, <1 a desirable. do not use the diode to charge a battery (especially lithium batteries!) there are two possible modes fo r battery backup operation; standard and legacy mode. in standard mode, there are no operational concerns when switch ing over to battery backup since all other devices function s are disabled. battery drain is minimal in standard mode, and return to normal v dd powered operations is predictable. in legacy mode, the v bat pin can power the chip if the voltage is above v dd and less than v trip . in this mode, it is possible to generate the alarm and communicate with the device, unless sbi = 1, but the supply current drain is much higher than the standard mode and backup time is reduced. in this case, if alarms are used in backup mode, the irq /f out pull-up resistor must be connected to v bat voltage source. alarm operation examples following are examples of both single event and periodic interrupt mode alarms. example 1 alarm 0 set with single interrupt (im = ?0?) a single alarm will occur on january 1 at 11:30am. a. set alarm 0 registers as follows: b. also the al0e bit must be set as follows: after these registers are set, an alarm will be generated when the rtc advances to exactly 11:30am on january 1 (after seconds changes from 59 to 00) by setting the al0 bit in the status register to ?1? and also bringing the irq/ f out output low. example 2 pulsed interrupt once per minute (im = ?1?) interrupts at one minute intervals when the seconds register is at 30 seconds. a. set alarm 0 registers as follows: b. set the interrupt register as follows: alarm0 register bit description 76543210hex sca0 00000000 00hsec onds disabled mna0 10110000 b0hminutes set to 30, enabled hra0 10010001 91hhours set to 11, enabled dta0 10000001 81hdate set to 1, enabled moa0 10000001 81hmonth set to 1, enabled dwa0 00000000 00hday of week disabled control register bit description 76543210hex int 00100000 x0he nable alarm figure 24. supercapacitor charging circuit v dd v bat v ss supercap 2.7v to 5.5v isl12026, isl12026a 22 fn8231.9 november 30, 2010 once the registers are set, the following waveform will be seen at irq/ f out : note that the status register al0 bit will be set each time the alarm is triggered, but does not need to be read or cleared. i 2 c communications during battery backup operation in battery backup mode is affected by the bsw and sbib bits as described earlier. these bits allow flexible operation of the serial bus an d eeprom in battery backup mode, but certain operational details need to be clear before utilizing the different modes. table 9 describes 4 different modes possible with using the bsw and sbib bits, and how they are affect the serial interface and battery backup operation. ? mode a - in this mode, selection bits indicate a standard mode switchover combined with i 2 c operation in battery backup mode. when the v dd voltage drops below the lower of v trip or v bat , then the device will enter battery backup mode. if the microcontroller and bus pull-ups are also powered by the battery, then the isl12026 can communicate in battery backup mode. ? mode b - in this mode, selection bits indicate legacy mode switchover combined with i 2 c operation in battery backup mode. when the v dd voltage drops below v bat , the device will enter battery backup mode. if the microcontroller and bus pull-ups are also powered by the battery, then the isl12026 can communicate in battery backup mode. this mode places the isl12026 device in the same operating mode as the x1226 legacy device. ? mode c - this mode combines standard mode battery switchover with no i 2 c operation in battery backup mode. when the v dd voltage drops below the lower of v trip or v bat , then the device will enter battery backup mode and the i 2 c interface will be disabled, minimizing v bat current drain. ? mode d - this mode combines legacy mode battery switchover with no i 2 c operation in battery backup mode. when the v dd voltage drops below v bat , the device will enter battery backup mode and the i 2 c interface will be disabled, minimizing v bat current drain. note that the irq /f out open drain output pin is active in battery backup for all modes, allowing clocking of devices while in battery backup mode. the pull-up on the pin will need to go to v bat , and thus battery mode current draw will increase accordingly. alarm0 register bit description 76543210hex sca0 10110000b0hseconds set to 30, enabled mna0 00000000 00hminutes disabled hra0 00000000 00hhours disabled dta0 00000000 00hdate disabled moa0 00000000 00hmonth disabled dwa0 00000000 00hday of week disabled control register bit description 76543210hex int 10100000 x0he nable alarm and int mode 60s rtc and alarm registers are both ?30? sec table 9. mode sbib bit bsw bit v bat switchover voltage i 2 c active in battery backup? ee prom write/ read in battery backup? freq/irq active? notes a 0 0 standard mode, v trip = 2.2v typ yes no yes, needs pull-up to v bat v bat switchover at lower of v bat or v trip . pull-ups needed on i 2 c to v bat to operate in battery backup. b (x1226 mode) 0 1 legacy mode, v dd < v bat yes no yes, needs pull-up to v bat v bat switchover at 24 fn8231.9 november 30, 2010 isl12026, isl12026a package outline drawing m8.173 8 lead thin shrink small outline package (tssop) rev 2, 01/10 notes: end view detail "x" typical recommended land pattern top view b a c plane seating 0.10 c 0.10 c b a h 3.0 0.5 4.40 0.10 0.25 +0.05/-0.06 6.40 0.20 c b a 0.05 0-8 gauge plane see detail "x" 0.90 +0.15/-0.10 0.60 0.15 0.09-0.20 6 3 4 2 4 1.00 ref 0.65 1.20 max 0.25 0.05 min 0.15 max (5.65) (0.65 typ) (0.35 typ) (1.45) 1 c l pin 1 id mark 4 5 8 package body outline side view 2. dimension does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall 3. dimension does not include interlead flash or protrusion. interlead flash or protrusion shall not exceed 0.15 per side. 4. dimensions are measured at datum plane h. not exceed 0.15 per side. 5. dimensioning and toleranc ing per asme y14.5m-1994. 6. dimension on lead width does not include dambar protrusion. allowable protrusion shall be 0.08 mm total in excess of dimension at maximum ma terial condition. minimum space between protrusion and adjacent lead is 0.07mm. 7. conforms to jedec mo-153, variation ac. issue e dimensions in ( ) for reference only. 1. dimensions are in millimeters. |
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